1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device and a method of testing the same.
2. Background Art
In the semiconductor device, TSV (Through-Silicon-Via) technology for providing a through electrode in a circuit board and laminating the circuit board is well known.
In TSV, through electrodes for connection can be arranged at an order interval of μ unit. Moreover, as a connecting distance is shorter than that of the known wire bonding, TSV can create benefits such as being less susceptible to noise, less delay, attenuation, and waveform degradation because of low parasitic capacitance and resistance, and eliminating the need for extra circuits for amplification and electrostatic discharge protection, thereby realizing circuits having a high-speed operation and low power consumption.
For example, Japanese Unexamined Patent Application Publication No. 2012-174826 discloses a semiconductor device including a through electrode that is formed of a continuous conductor extending through two or more substrates.
FIGS. 6A to 7B are diagrams showing a manufacturing process of a semiconductor chip 100.
FIG. 6A is a diagram showing a state in which a transistor 102 and TSVs 110a and 110b are formed in and above the semiconductor chip 100. The TSVs 110a and 110b are formed when the transistor 102 is formed.
Next, as shown in FIG. 6B, a wiring layer 103 and wafer test pads 104 are formed above the semiconductor chip 100. Then, the transistor 102 is tested using the wafer test pads 104. As the TSVs 110a and 110b are buried in a silicon substrate and not connected to a closed circuit, continuity of the TSVs 110a and 110b cannot be tested.
FIG. 7A is a diagram showing a thinned semiconductor chip 100. The semiconductor chip 100 is thinned, and micro bumps 105 are connected to lower surfaces of the TSVs 110a and 110b. 
FIG. 7B is a diagram showing a laminated semiconductor chip 100. The semiconductor chip 100 is laminated above another semiconductor chip 107 using micro bumps 105 for connecting it to the semiconductor chip 107, eventually completing a three-dimensional LSI.
As for a semiconductor chip having a non-penetrating TSV (hereinafter referred to as a via-middle style) like the one shown in FIGS. 6A and 6B, since a lower part of the TSV is buried in a silicon substrate 115, the wafer test pads 104 cannot detect a failure.
Moreover, the TSV will penetrate the silicon substrate 115 after thinning processing in a lamination process, however as a pitch between the micro bumps is extremely small and the wafer is extremely thin, it is particularly difficult to conduct a wafer test.
Therefore, when the semiconductor chip 100 including a via-middle TSV is tested, it has been necessary to conduct the test after the semiconductor chip 100 is laminated, using a test circuit or the like for the semiconductor chip 107 that is a laminated layer.
However, the present inventor has found a problem that when a test is conducted after lamination, if at least one TSV has a failure in the laminated chips, the entire laminated semiconductor device including laminated semiconductor chips besides those in which the at least one TSV has a failure will be defective, thereby increasing the manufacturing cost.